1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to the semiconductor device in which a system constructed by connecting, through buses and/or signal lines, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM (Random Access Memory), a plurality of signal processing circuits adapted to process a variety of signals or a like, is integrated into one semiconductor chip.
The present application claims priority of Japanese Patent Application No.2000-035930 filed on Feb. 14, 2000, which is hereby incorporated by reference.
2. Description of the Related Art
In recent years, as semiconductor devices such as an LSI (Large Scale Integrated circuit) or a like become highly integrated and as their packaging densities increase, a semiconductor on which one million or more transistors are mounted can be implemented. One example is a SOC (System On a Chip) in which a system constructed of a CPU, ROM, RAM, a plurality of digital signal processing circuits or a like each being connected through buses to each other, is incorporated into one semiconductor chip. For example, in a literature entitled xe2x80x9cEmbedded DRAM Macro for ASICxe2x80x9d (Shinji Miyano, Toshiba Review, Vol. 52, No.12. pp.15-18, 1997), a semiconductor device is disclosed in which a system constructed by connecting a DRAM (Dynamic Random Access Memory) having a large capacity memory and a digital signal processing circuit to process a variety of digital signals through buses is incorporated into one semiconductor chip. The semiconductor device of this kind has an advantage in that, since both the memory and digital signal processing circuit are formed on a same semiconductor chip, data can be transferred through buses each having a wider width for transmission and at a higher transmission speed between the memory and the digital signal processing circuit and also a mounting area on a printed circuit board (PCB) can be more reduced, unlike a case where the DRAM formed on an independent chip and encapsulated in an independent package is connected to LSIs containing digital signal processing circuits through pins and through patterns formed on a PCB.
However, since the SOC described above is large in scale, direct design at a transistor level is impossible. To solve this problem, system design to define operations or to decide configurations of a whole system, logical design to decide relations among functional blocks and to define operations within each of functional blocks in accordance with specifications decided by the system design, detail logic design to configure each of the functional blocks by combining logical devices such as NAND gates, NOR gates, latches, counters or a like and circuit design to decide characteristics of electronic circuits and elements so as to meet circuit specifications based on the logical design are sequentially performed, in stages, so that each of the CPUs, ROMs, RAMs or the plurality of digital signal processing circuits adapted to perform specified digital processing or a like can implement its desired functions as one functional block. Moreover, since the semiconductor device is generally expected to be embedded in various electronic devices, it is required that its development period is as short as possible. Therefore, in order to implement facilitation of the system design and shortening of development period, memories making up the SOC have to have general versatility which allows memories mounted on the SOC to be constructed by freely and flexibly combining a plurality of memory blocks containing memory cell arrays having specified memory capacities, sense amplifiers or a like, depending on desired storage capacities, the number of banks, the number of rows of memory cell arrays to be refreshed, or a like. In the above technical literature, there is also a description about such general versatility required in a unit configuration of a DRAM core.
However, since the memory making up the SOC is provided with not only memory blocks but also peripheral devices including input/output circuits used to input or output data to the memory blocks, control circuits generating various control signals used to input or output data to specified cells of the memory arrays making up the memory blocks, in order to achieve facilitation of system design and shortening of development period, it is required that such peripheral devices have such general versatility as described above. Though the above technical literature describes general versatility, however, it describes neither configurations of peripheral devices nor the general versatility required in the peripheral devices.
Thus, even if a system designer can design so that the memory making up the SOC is constructed by combing a plurality of memory blocks depending on desired storage capacities, the number of banks, the number of rows of memory cell arrays to be refreshed or the like, the system designer has to perform separate design of such peripheral devices, which causes a limitation on facilitation of the system design and shortening of development time.
In view of the above, it is an object of the present invention to provide a semiconductor device having a memory provided with a peripheral device which can operate in a versatile manner, irrespective of combinations of memory capacity, numbers of banks, numbers of rows of memory cell arrays to be refreshed or a like.
According to a first aspect of the present invention, there is provided a semiconductor device including:
a memory to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein the memory includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of the memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of the blocks making up the memory block according to pre-set storage capacity and/or numbers of banks.
In the foregoing, a preferable mode is one wherein the activating circuit outputs, according to pre-set storage capacity and/or numbers of banks, a block selecting signal used to select any one of blocks making up the memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to the memory cell array in a selected state based on the decoded row address, a main-word timing control signal used to control timing with which the row decoder outputs the main-word activating signal and a sub-word activating signal used to activate a sub-word line of the memory cell array making up the corresponding block, to each of a plurality of the blocks making up the memory block.
Also, a preferable mode is one that wherein includes a control circuit which generates, according to pre-set storage capacity and/or numbers of banks and based on an address supplied from outside, a latch signal used to temporarily latch the block selecting signal, a first control signal used to control timing with which the row address latch signal is output, a second control signal used to control timing with which the activating circuit outputs the main-word timing control signal, a third control signal used to control timing with which the activating circuit outputs the sub-word activating signal, a capacity mode signal corresponding to pre-set storage capacity and a bank mode signal corresponding to numbers of banks and then feeds these signals to the activating circuit with specified timing, wherein the activating circuit, based on the latch signal, the first to third control signals, the capacity mode signal and the bank mode signal, generates the various activating signals.
Also, a preferable mode is one wherein the control circuit, when a test on the memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in the test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in the blocks and feeds these signals to the activating circuit, wherein the activating circuit, based on the test mode signal, the test clock and the block forcedly-activating signal, generates various activating signals.
Furthermore, a preferable mode is one wherein the memory cell array has a storage capacity of 1M bits and has a plurality of memory cells arranged in a matrix-like manner and in 512 rowsxc3x972048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits and numbers of banks that are allowed to be set include any one of 1, 2 and 4.
According to a second aspect on the present invention, there is provided a semiconductor device including:
a DRAM (Dynamic Random Access Memory) to store various data and to be embedded in one semiconductor chip together with circuits to process various signals, wherein the DRAM includes a memory block in which a plurality of blocks, being corresponded to pre-set storage capacity of the memory block, made up of a memory cell array having predetermined storage capacity and being constructed of a plurality of memory cells is arranged and of first and second sense amplifiers constructed so as to sandwich the memory cell array and used to detect data read to a bit line from the memory cell making up the memory cell array and to amplify the data and an activating circuit configured so as to correspond to numbers of blocks satisfying maximum settable storage capacity which outputs a variety of activating signals used to activate a plurality of the blocks making up the memory block according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed representing numbers of rows of the memory cell arrays to be activated by one time refreshing processing.
In the foregoing, a preferable mode is one wherein the activating circuit outputs, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays, a block selecting signal used to select any one of blocks making up the memory block, a row address latch signal used to temporarily latch a row address decoded by a row decoder which outputs a main-word activating signal to put a main-word line corresponding to the memory cell array in a selected state, based on the decoded row address, a main-word timing control signal used to control timing with which the row decoder outputs the main-word activating signal, a sub-word activating signal used to activate a sub-word line of the memory cell array making up the corresponding block and a sense amplifier activating signal used to activate two sense amplifiers making up the corresponding block, to each of a plurality of the blocks making up the memory block.
Also, a preferable mode is one that wherein includes a control circuit which generates, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed and based on an address supplied from outside, a latch signal used to temporarily latch the block selecting signal, a first control signal used to control timing with which the row address latch signal is output, a second control signal used to control timing with which the activating circuit outputs the main-word timing control signal, a third control signal used to control timing with which the activating circuit outputs the sub-word activating signal, a fourth control signal used to control timing with which the activating circuit outputs the sense amplifier activating signal, a capacity mode signal corresponding to pre-set storage capacity, a bank mode signal corresponding to numbers of banks, a refresh mode signal corresponding to pre-set numbers of rows of memory cell arrays to be refreshed and then feeds these signals to the activating circuit with specified timing, wherein the activating circuit, based on the latch signal, the first to fourth control signals, the capacity mode signal, the bank mode signal and the refresh mode signal, generates various activating signals.
Also, a preferable mode is one wherein the activating circuit includes a refresh decoder to decode data obtained by combining higher-order bits contained in the refresh mode signal with those contained in the row address and to generate a block activating designation signal used to designate the block to be activated and a block activating section mounted in numbers corresponding to numbers of blocks satisfying maximum settable capacity, to generate, based on the latch signal, a reversed latch signal obtained by reversing the latch signal, the first to fourth control signals, the capacity mode signal, the bank mode signal and the refresh mode signal, according to pre-set storage capacity, numbers of banks and numbers of rows of memory cell arrays to be refreshed, with specified timing, the block selecting signal and generates the row address latch signal, the main-word timing control signal, the sub-word activating signal and the sense amplifier activating signal.
Also, a preferable mode is one wherein the block activating section includes a block selecting signal generating circuit which generates, based on the block activating designation signal, the latch signal, the reversed latch signal, the refresh mode signal and the bank mode signal, a block selecting signal used to designate the corresponding block, a row address latch signal generating circuit which generates, based on the first control signal and the block selecting signal, the row address latch signal and feeds it to corresponding one contained in the blocks and an activating signal generating circuit which generates, based on the second to fourth control signals and the block selecting signal, the sub-word activating signal and the sense amplifier activating signal and the main-word timing control signal and feeds these signals to corresponding blocks.
Also, a preferable mode is one wherein the control circuit, when a test on the memory is executed, generates a test mode signal used to put all banks in a test mode, a test clock being a clock used in the test mode and a block forcedly-activating signal used to forcedly activate corresponding one block contained in the blocks and feeds these signals to the activating circuit, wherein the activating circuit, based on the test mode signal, the test clock and the block forcedly-activating signal, generates the various activating signals.
Furthermore, a preferable mode is one wherein the memory cell array has a storage capacity of 1M bits and has a plurality of memory cells arranged in a matrix-like manner and in 512 rowsxc3x972048 columns form and wherein storage capacity that is allowed to be set includes any one of 1M, 2M, 4M and 8M bits, numbers of banks that are allowed to be set include any one of 1, 2 and 4 and numbers of rows of memory cell arrays to be refreshed that are allowed to be set include any one of 512, 210, 211 and 212.
With the above configuration, since the memory or the DRAM embedded in the one semiconductor chip of the present invention is provided with the memory block in which a plurality of blocks each being made up of one memory cell array having predetermined storage capacity or a plurality of blocks each being made up of one memory cell array and of first and second sense amplifiers between which the memory cell array is sandwiched, is arranged according to pre-set storage capacity of the memory block and with activating circuits so configured as to correspond to the block having the number satisfying the maximum settable storage capacity and output a variety of activating signals used to activate the two or more blocks making up the memory block according to the pre-set storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed, system designer, even when combinations of the storage capacity, the number of banks and the number of rows of memory cell arrays to be refreshed are changed, can freely and easily perform system design of the memory of the semiconductor device. This also allows system design of the semiconductor device to be made easier and development period of the semiconductor device to be shortened.
With another configuration as above, since the activating circuit, according to the pre-set storage capacity and/or the number of banks and for each of the two or more blocks, generates the row address latch signal used to temporarily hold the row address decoded by the row decoder and the block selecting signal used to select one of blocks making up the memory block and since the control circuit generates the latch signal used to temporarily hold the block selecting signal, it is possible to perform multi-banking operations in which a plurality of blocks belonging to a plurality of banks is simultaneously activated.
With still another configuration as above, since the control circuit generates the test mode signal, test clock and block forcedly-activating signal and the activating circuit, based on the test mode signal, test clock and block forcedly-activating signal, generates various activating signals, it is possible to execute the reliability test on the memory.